As is well known, in a CDMA2000 1X base station transmit system, a Digital Up-converter Card Assembly (DUCA) is used to generate 58.9824 MHz clock pulses. These pulses are used to perform all signal processing based on 19.6608 MHz reference clock pulses.
As is shown in FIG. 1, a conventional clock generator using a Phase Locked Loop (PLL) is configured to generate 58.9824 MHz clock pulses in which their phase is locked with a 19.6608 MHz by PLL 10. PLL 10 comprises a phase detector 11, a low pass filter 12, and a Voltage Controlled Oscillator (VCO) 13.
However, when the clock pulses are generated using a conventional clock generator with PLL 10 such as the one described above, the output clock frequency cannot vary in accordance with system performance. This is because the output clock frequency is fixed. Further, the quality of the output clock signal may become degraded due to jitter and phase noise.